Programming docs for the PSIC ps/2 communication chip

This document is freely distributable as long as it is not changed, and one
of the sources www.jschoenfeld.com, www.jschonfeld.de, www.siliconsonic.com
is mentioned. 

last update: March 6th, 2001

General
-------
PSIC is a ps/2 host interface communication chip designed by individual
Computers. It can communicate semi-bi-directional with any PS/2 mouse or
MF2 keybaord. Parity checking/generating is done by the hardware. The chip
has a 1-byte buffer for incoming data, and another byte for outgoing data.
Handshaking with the device is done in hardware, so even in highly-loaded
multitasking enviroments, no data will be lost due to late IRQ serving. IRQs
can be generated for incoming data if enabled in the command register. A
status register will give detailed information about what the chip is doing
at the moment, and about buffer status.
Although the PS/2 interface is only specified for 10KBaud to 33KBaud
communication, the PSIC can handle data rates of up to 175 KBits per second.

Electrical
----------
The host interface is a combined Intel/Motorola interface. This means, 
Intel I/O timing is used for processor accesses, but the reset and IRQ pins
are active-low, just like Motorola processors require. An inactive IRQ is
represented by a free-floating line (high-z), making the device capable of
shared IRQs.

A chip reset stops all communication with ps/2 devices and resets all
internal state machines. Reset also disables the host interface, so
accidential CS, IOR or IOW assertion during reset does not affect the bus.
Further, any pending IRQ is deasserted, and IRQs will be disabled. This
ensures that the chip will not issue any IRQ until the drivers have
initialized the chip, thus maximizing system-startup reliability. Read and
write accesses can be both, CS-triggered or IOR/IOW triggered. Accesses
should be at least 30ns long to ensure that the data has come through all
gates that may cause a propagatin delay, including external host buffers.
This is met in all existing Amiga circuits, including the high-speed timing
that is generated be the Maxxler chip.

Optional higher-order address lines and chip-select outputs eliminate the
need for glue logic on the board.

Registers
---------
One address line selects one of two registers:

0: Data register
Writing to this register will write to the output buffer and start a
host-to-device communication.

Reading this register will read the input buffer and enable further incoming
data. Caution: You can only read this register once, it may already be
overwritten on the next read!

1:
Write: IRQ enable/auxilary output register:
Bits 0-2: Auxilary output bits. The value of these bits is represented on the
          three auxilary output pins. Caution: A write to register 0 will
          reset these bits! 
Bit 7: A 1 in this bit will enable IRQs for incoming pending data. 
Writing to this register also disables all running communication, reading or
writing. this can be used for re-syncing to the device after a hot-plug or a
cable failure. Caution: If a proper communication is stopped, the state
machines may get stuck in an undefined state. Make sure that the device is not
active communicating before writing to this register!
                                                     
Read: Status register
Bit 0: Auxilary input bit (pin status)
Bit 1: Current status of PS/2 clock line
Bit 2: Current status of PS/2 data line
Bit 3 is unused
Bit 4: DataPending. This bit is set when valid data is contained in the input
       buffer. It is reset automatically on reading the input buffer.
Bit 5: Active writing: This bit is set during host-to-device communication.
Bit 6: Active: This bit is set during any communication on the PS/2 bus.
Bit 7: IRQ: This bit is set if an issued IRQ comes from this chip.

Access procedures
-----------------
Chip-init:
Read status register. If Data Pending bit is set, read data register, store
the value (it may be required by handler software). Repeat until Data Pending
bit is not set for more than 2ms, or more than 16 bytes have been read. Also
check Active bit during this procedure: If no data is pending, check active.
If active is not set, proceed with initialize, if active is set, timeout
after 32ms. Always read pending data in this procedure!
Quick end of this procedure: If chip is not active, data is not pending, and
both PS2DAT and PS2CLK are set, the bus is idle. Proceed with initialize in
this case.

Write the IRQ enable register with the value you need. Then check for idle
bus; if idle, initialize is finished. If not idle, repeat init procedure for
a reasonable amount of times.

reading a byte from a PS/2 device:
Read Status register. If Data Pending bit is set, read data register.

Handling IRQs:
Read Status register, check for IRQ bit set. If not set, leave IRQ service
routine. If set, check Data Pending bit. If set, read data register. To check
Data Pending bit, no further read is necessary! Use the value you have read
at the beginning of this procedure. An additional read would only be a waste
of CPU time, as I/O accesses are slower than CPU-internal accesses.


writing a byte to a PS/2 device:
Check for idle bus (not active, no data pending), if idle, write byte to Data
register.

If you have any comments or questions, send me an e-mail: jens@jschoenfeld.de
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