Programming docs for the VarIO interface board

This document is freely distributable as long as it is not changed, and one
of the sources www.jschoenfeld.com, www.jschonfeld.de, www.siliconsonic.com
or www.siliconsonic.de is mentioned. 

last update:
January 7th, 2002   (added register numbers for use on 26-pin ports)
December 1st, 2001  (bad documentation by Exar! chaged the design, updated
                     parallelport register table)
November 28th, 2001 (added comments about timing diagrams)
November 22nd, 2001 (added interrupt documentation)
November 20th, 2001 (initial version after major change of hardware)

Vendor number: 4626 ($1212)
product number: 7
Serial number: 1

The board supports the "shutup_forever" option.

Note: serial number 0 has been used for the prototype board that was
initially planned in march 2001. That version with Maxxler chip and PAOLA
parallelport will not be made. The combination Maxxler and PAOLA is fast,
but the 78C36a ECP port is faster with it's Fifo memory. PS2 has been dropped
completely, because we already have solutions for mice and keyboards.
I focused on flexibility of interfacing the computer instead.

Memopry map:

If used in Zorro mode, VarIO is a 64K Zorro board. The red LED is on when in
Zorro mode. All addresses are to be added to the board offset:

$0000-$7fff     Config-Nibbles
$8000-$803f     clock-port or sub-VarIO
                if a sub-VarIO is connected to the 26-pin port, the sub-serial
                is at $8020, and the sub-parallel is at $8000.
$8040-$805f     parallel port (ST78C36a)
$8060-$807f     serial port (16c550)

If VarIO is used on a clock-port, the red LED is off (Add-On mode):

clockport+$00   parallel port
clockport+$20   serial port

Note: On the A600 Silversurfer-adapter, the register spacing is different,
therefore the serial port starts at clockport+$8000. 

You could also think of using a sub-VarIO on the clock-port, but this would
be a waste of money: The clockport version has a more expensive RS232 driver
(the +5V only type), and the cable is more expensive. Use the included 26-pin
cable instead, it also gives the +/-12V lines to the sub-board. Only one of
the expansion ports can be used, either the clockport, or the 26-pin port,
but not both at the same time!

The parallel port is a Startech/Exar ST78C36a EPP/ECP parallel port with 16
byte Fifo, clocked at 24Mhz. The EPP function can only be used on this board
with banking, because the EPP-DPort is only available for the software with
a write to the Modem Control register of the 16c550 UART chip. The
banking-bit is "out2" bit of the Modem Control register (bit 3). After a
reset, it is set to 0, so the EPP-DPorts are visible, and no other parallel
port registers can be accessed. Program bit 3 of MCR to "1" to have the
correct parallel port register map!

The serial port is a California Micro Devices CM16c550PE, clocked at
7,3728 Mhz, just like on the Silversurfer. Existing drivers should be
adapted pretty quickly, because even the address spacing is the same!
The datasheet of that chip is not available in electronic form (PDF or
something). However, I managed to get a hardcopy from California Micro
directly. If you need a copy, send me an eMail. For other questions, consult
the Startech 16c550 PDF file, it describes a software compatible chip.

** note: None of individual Computers' designs uses the out2 bit of the MCR.
** it is recommended to initialize all UARTs with bit 3 of MCR set to 1 in
** order to avoid clashes with the parallel port on the VarIO. I want to
** make the access possible, however, I don't expect anyone to use this
** feature.

Individual registers:

parallel port (offset plus register) with bit 3 of MCR=1:

$00     Data/ECP-AFIFO         (A600 adapter: $0000)
$04     DSR                    (A600 adapter: $1000)
$08     DCR                    (A600 adapter: $2000)
$0c     EPP-APort              (A600 adapter: $3000)
$10     CONF-A                 (A600 adapter: $4000)
$14     CONF-B                 (A600 adapter: $5000)
$18     ECR (extended control) (A600 adapter: $6000)

parallel port (offset plus register) with bit 3 of MCR=0:

$00     EPP-D Port register A  (A600 adapter: $0000)
$04     EPP-D Port register B  (A600 adapter: $1000)
$08     EPP-D Port register C  (A600 adapter: $2000)
$0c     EPP-D Port register D  (A600 adapter: $3000)

serial port (for register names, see Inside_Surfer.txt):

$00     Register 0   (A600 adapter: $0000)
$04     Register 1   (A600 adapter: $1000)
$08     Register 2   (A600 adapter: $2000)
$0c     Register 3   (A600 adapter: $3000)
$10     Register 4   (A600 adapter: $4000)
$14     Register 5   (A600 adapter: $5000)
$18     Register 6   (A600 adapter: $6000)
$1c     Register 7   (A600 adapter: $7000)

If VarIO is used on a 26-pin expansion port on one of our Zorro boards,
the red LED is off as well.
--
Register spacing on the 26-pin ports of one of our Zorro-cards is totally
different. The following list applies to these boards:

Buddha
Buddha Flash
Catweasel Z-II (all versions)
ISDN Surfer
X-Surf

It does *not* apply to the "VarIO on VarIO" combination. See the "sub-VarIO"
parts of the memory map chapter of this document for those registers.

Parallelport registers: (26-pin offset plus register)

$58     Data/ECP-AFIFO
$5a     DSR
$5c     DCR
$5e     EPP-APort
$78     CONF-A
$7a     CONF-B
$7c     ECR (extended control)

Serial port registers: (26-pin offset plus register)

$d8     Register 0
$da     Register 1
$dc     Register 2
$de     Register 3
$f8     Register 4
$fa     Register 5
$fc     Register 6
$be     Register 7 (this is not a typo! Really $be, not $fe!)

--

Interrupts:

Both ports (serial and parallel) issue an IRQ6. The IRQ line of the 16c550
is directly translated to IRQ6 with no additional logic in between (just like
the Silversurfer). If used in a Zorro slot, IRQs are disabled until the
autoconfig procedure has been passed, this ensures system stability.

The ST78C36 has several IRQ lines. VarIO only uses IRQ line number 7 (pin 19
of the PLCC44 package). For IRQs to be passed properly to the Amiga, the chip
must be configured to use this IRQ line. All other IRQ configs will not work
with VarIO!

The parallelport chip has strobed IRQs that would be too short for certain
multitasking applications. VarIO stores a strobed IRQ in a flipflop, and
holds IRQ6 until it is served by the software. The flipflop is cleared by any
access to the parallelport chip, including the unused register $1c of that
chip. The access can either be a read or a write access.

VarIO gives no additional possibilities to tell whether an IRQ has been
issued by a certain port or not. See the chip documentation for these
functions.

clockport timing:

If you want to design hardware that works properly on the clockport of VarIO,
take a look at the two pictures VarIO_IOW.gif and VarIO_IOR.gif. Both are
snapshots from an Agilent mixed-signal scope in Logic Analyzer mode. Speed is
50ns per div, the labels should be self-explanatory. The two data lines
and the three address lines give enough information about the rest of the bus:

write access:

Addresses are valid thoughout the cycle, they are stable for more than 50ns
before the cycle, and they remain valid at least 40ns after the cycle. Do
not rely on the address lines staying valid after deassertion of SEL! The
end of the Zorro cycle is detected by deassertion of AS (address strobe),
so it is very likely that accelerator cards do a change of address lines
fairly quick after AS=high (especially in A2000 computers).

Data becomes valid about 25ns after cycle start, and remains valid at least
40ns after the cycle.

IOW is asserted about 140ns after cycle-start, and is deasserted after about
200ns. A whole cycle is about 350ns long.

read access:

Addresses are valid thoughout the cycle, they are stable for more than 50ns
before the cycle, and they remain valid at least 40ns after the cycle. Do
not rely on the address lines staying valid after deassertion of SEL! The
end of the Zorro cycle is detected by deassertion of AS (address strobe),
so it is very likely that accelerator cards do a change of address lines
fairly quick after AS=high (especially in A2000 computers).

Data lines are 3-stated, and should be driven by your hardware as fast as
possible. Consult a 68K manual for minimum access times and the exact point
where the CPU samples the data.

IOR is asserted with the beginning of the cycle (together with SEL), and it
is deasserted at the end of the cycle, also together with SEL. 

If you have any questions, feel free to write me an eMail:
jens@jschoenfeld.de

--EOF