Documentation for the Maxxler chip

This document is freely distributable as long as it is not changed, and one
of the sources www.jschoenfeld.com, www.jschonfeld.de, www.siliconsonic.com
is mentioned. 

last update: April 9th, 2001

General
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Maxxler is a load-balancing chip that allows 16-bit wide accesses to 8-bit
wide hardware. This is accomplished by bi-directional routing and storing of
the transferred word. At the same time, Intel IOR/IOW timing is generated
from Motorola busses. Special versions are available that support non-Intel
Hardware, like the host-bus of the 56K DSP.
The access can be a read or write cycle. Both are translated to double-speed
8-Bit cycles. The double-access is generated on-demand, so slow hardware like
serial UARTs is also supported. If a double-access is demanded, the two
accesses can either be made to one register of the destination chip, or to
two consecutive registers.

Electrical
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Maxxler has two databusses, one 8-bit bus for periphal chips, and one 16-bit
bus for the host side. Timing on the host side is designed for Motorola-like
interfaces. Two inputs "Double" and "consec" demand double-speed access and
generation of an inverted address signal for consecutive addresses. The two
inputs should be connected to higher-order address lines, so mirrors of the
periphal chips act as 16-bit mirrors with special features.

Generating the consecutive addresses is NOT an arithmetical operation.
Instead, only one address line is inverted between the two accesses. Example:
Assuming you have fed the lowest address line of the periphal chip into
Maxxler, word-access to address register 0 will do byte-accesses to 0,
then to 1. On the other hand, an access to register 1 will  first access
register 1, then 0.

To generate Intel-IO Timing this fast, a 40 Mhz asyncronous clock is needed.
Pulse width on IOR is longer than IOW, only the sample times for data is
different. Pulse width on double-speed accesses at least 100ns, with a 75ns pause
between the two accesses. IOR is held until the end of the 68K cycle, IOW is
deasserted during data valid on the 8-bit side. Make sure that your hardware
supports this speed! Hardware that is known to support the speed is: The PAOLA 
parallel port chip, and the Melody sound card for the A1200. On Byte-accesses,
pulse width is at least 325ns. Data is sampled frequently over read accesses,
data sample time for a write cycle is on the beginning of a pulse. Make sure
that your periphals do not require stable data before a write pulse begins!

It is recommended to buffer the two data busses. However, if there is no
cable between Maxxler and the 8-bit periphal, a number of CMOS loads can be
driven by Maxxler.

Registers
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Maxxler has no registers. 

If you have any questions, feel free to ask me via e-mail:
jens@jschoenfeld.de
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